View CY14B104LA-ZS25XIT_5098978.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy14b104la, cy14b104na 4-mbit (512 k 8/256 k 16) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-49918 rev. *j revised september 30, 2011 4-mbit (512 k 8/256 k 16) nvsram features 20 ns, 25 ns, and 45 ns access times internally organized as 512 k 8 (cy14b104la) or 256 k 16 (cy14b104na) hands off automatic store on power-down with only a small capacitor store to quantumtrap non-volatile elements initiated by software, device pin, or autostore on power-down recall to sram initiated by software or power-up infinite read, write, and recall cycles 1 million store cycles to quantumtrap 20 year data retention single 3 v +20 % , ?10 % operation industrial temperature packages ? 44-/54-pin thin small outline package (tsop) type ii ? 48-ball fine-pitch ball grid array (fbga) pb-free and restriction of hazardous substances (rohs) compliant functional description the cypress cy14b104la/cy14b104na is a fast static ram (sram), with a non-volatile element in each memory cell. the memory is organized as 512 k bytes of 8 bits each or 256 k words of 16-bits each. the embedded non-volatile elements incorporate quantumtrap technology, producing the world?s most reliable non-volatile memory. the sram provides infinite read and write cycles, while independent non-volatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the non-volatile elements (the store operation) takes place automatically at power-down. on power-up, data is restored to the sram (the recall operation) from the non-volatile memory. both the store and recall operations are also available under software control. static ram array 2048 x 2048 r o w d e c o d e r column i/o column dec i n p u t b u f f e r s power control store/recall control quatrum trap 2048 x 2048 store recall v cc v cap hsb a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 software detect a 14 - a 2 oe ce we bhe ble a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 17 a 18 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 logic block diagram [1, 2, 3] notes 1. address a 0 ?a 18 for 8 configuration and address a 0 ?a 17 for 16 configuration. 2. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 3. bhe and ble are applicable for 16 configuration only.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 2 of 25 contents pinouts .............................................................................. 3 pin definitions .................................................................. 4 device operation .............................................................. 5 sram read ....................................................................... 5 sram write ....................................................................... 5 autostore operation ........................................................ 5 hardware store operation ............................................ 5 hardware recall (power-up) ....................................... 6 software store ............................................................... 6 software recall ............................................................. 6 preventing autostore ....................................................... 7 data protection ................................................................. 7 noise considerations ....................................................... 7 best practices ................................................................... 8 maximum ratings ............................................................. 9 operating range ............................................................... 9 dc electrical characteristics .......................................... 9 data retention and endurance ..................................... 10 capacitance .................................................................... 10 thermal resistance ........................................................ 10 ac test loads ................................................................ 10 ac test conditions ........................................................ 10 ac switching characteristics ....................................... 11 switching waveforms .................................................... 11 autostore/power-up recall ....................................... 14 switching waveforms .................................................... 14 software controlled store/recall cycle ................ 15 switching waveforms .................................................... 15 hardware store cycle ................................................. 16 switching waveforms .................................................... 16 truth table for sram operations ................................ 17 ordering information ...................................................... 18 ordering code definitions ..... .................................... 19 package diagrams .......................................................... 20 acronyms ........................................................................ 23 document conventions ......... .................................... 23 units of measure ....................................................... 23 document history page ................................................. 24 sales, solutions, and legal information ...................... 25 worldwide sales and design s upport ......... .............. 25 products .................................................................... 25 psoc solutions ......................................................... 25
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 3 of 25 pinouts figure 1. pin diagram ? 48-ball fbga figure 2. pin diagram ? 44-pin tsop ii we v cc a 11 a 10 v cap a 6 a 0 a 3 ce nc nc dq 0 a 4 a 5 nc dq 2 dq 3 nc v ss a 9 a 8 oe v ss a 7 nc nc nc a 17 a 2 a 1 nc v cc dq 4 nc dq 5 dq 6 nc dq 7 nc a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 a 18 nc dq 1 [4] we v cc a 11 a 10 v cap a 6 a 0 a 3 ce dq 10 dq 8 dq 9 a 4 a 5 dq 13 dq 12 dq 14 dq 15 v ss a 9 a 8 oe v ss a 7 dq 0 bhe nc a 17 a 2 a 1 ble v cc dq 2 dq 1 dq 3 dq 4 dq 5 dq 6 dq 7 a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 nc nc dq 11 (not to scale) top view ( 16) [4] 48-ball fbga 48-ball fbga (not to scale) top view ( 8) nc a 8 nc nc v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 a 17 a 18 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-pin tsop ii top view (not to scale) a 10 nc we dq 7 hsb nc v ss v cc v cap nc ( 8) [4] [5] v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 ble a 9 ce a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 11 a 10 a 14 bhe oe a 15 a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-pin tsop ii top view (not to scale) we dq 7 a 0 v ss v cc dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 v cap ( 16) ( 16) ( 8) [6] notes 4. address expansion for 8-mbit. nc pin not connected to die. 5. address expansion for 16-mbit . nc pin not connected to die. 6. hsb pin is not available in 44-pin tsop ii ( 16) package.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 4 of 25 figure 3. pin diagram ? 54-pin tsop ii ( 16) pin definitions pin name i/o type description a 0 ?a 18 input address inputs. used to select one of the 524,288 byte s of the nvsram for 8 configuration. a 0 ?a 17 address inputs. used to select one of the 262,144 words of the nvsram for 16 configuration. dq 0 ?dq 7 input/output bidirectional data i/o lines for 8 configuration . used as input or output li nes depending on operation. dq 0 ?dq 15 bidirectional data i/o lines for 16 configuration . used as input or output lines depending on operation. we input write enable input, active low . when selected low, data on the i/o pins is written to the specific address location. ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. i/o pins are tristated on deasserting oe high. bhe input byte high enable, active low . controls dq 15 ?dq 8 . ble input byte low enable, active low . controls dq 7 ?dq 0 . v ss ground ground for the device . must be connected to the ground of the system. v cc power supply power supply inputs to the device . hsb [9] input/output hardware store busy (hsb ) . when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a non-volatile store operation. after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current, and then a weak internal pull-up resistor keep s this pin high (external pull-up resistor connection optional). v cap power supply autostore capacitor . supplies power to the nvsram during power loss to store data from sram to non-volatile elements. nc no connect no connect . this pin is not connected to the die. pinouts (continued) a 17 dq 7 dq 6 dq 5 dq 4 v cc dq 3 dq 2 dq 1 dq 0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 a 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54-pin tsop ii top view ( not to scale) oe ce v cc nc v ss nc a 9 nc nc nc nc nc nc 54 53 52 51 49 50 hsb bhe ble dq 15 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 ( 16) [8] [7] notes 7. address expansion for 16-mbit. nc pin not connected to die. 8. address expansion for 8-mbit . nc pin not connected to die. 9. hsb pin is not available in 44-pin tsop ii ( 16) package.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 5 of 25 device operation the cy14b104la/cy14b104na nvsram is made up of two functional components paired in the same physical cell. they are a sram memory cell and a non-volatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the non-volatile cell (the store operation), or from the non-vo latile cell to the sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and writ e operations are inhibited. the cy14b104la/cy14b104na supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the non-volatile cells and up to 1 million store operations. refer to the truth table for sram operations on page 17 for a complete description of read and write modes. sram read the cy14b104la/cy14b104na performs a read cycle when ce and oe are low and we and hsb are high. the address specified on pins a 0?18 or a 0?17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit word s. when the read is initiated by an address transition, the output s are valid after a delay of t aa (read cycle 1). if the r ead is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need fo r transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?15 are written into the memory if the data is valid (t sd time) before the end of a we controlled write or be fore the end of an ce controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16-bit words. it is recom- mended that oe be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b104la/cy14b104na stores data to the nvsram using one of the following three storage operations: hardware store activated by the hsb ; software store activated by an address sequence; autostore on device power-down. the autostore operation is a uni que feature of quantumtrap technology and is enabled by default on the cy14b104la/cy14b104na. during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. note if the capacitor is not connected to v cap pin, autostore must be disabled using the soft sequence specified in preventing autostore on page 7 . in case autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without sufficient char ge to complete the store. this corrupts the data stored in nvsram. figure 4 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 9 for the size of v cap . the voltage on the v cap pin is driven to v cc by a regulator on the chip. a pull-up should be placed on we to hold it inactive during power-up. this pull-up is effective only if the we signal is tristate during power-up. many mpus tristate their controls on power-up. this should be verified when using the pull-up. when the nvsram comes out of power-on-recall, the mpu must be active or the we held inactive until the mpu comes out of reset. to reduce unnecessary non-volatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the syst em to detect if an autostore cycle is in progress. figure 4. autostore mode hardware store operation the cy14b104la/cy14b104na provides the hsb [10] pin to control and acknowledge the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the cy14b104la/cy14b104na conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is inter- nally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by internal 100 k pull-up resistor. 0.1 uf v cc 10 kohm v cap we v cap v ss v cc note 10. hsb pin is not available in 44-pin tsop ii ( 16) package.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 6 of 25 sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiat ed. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. in case the write latch is not set, hsb is not driven low by the cy14b104la/cy14b104na. but any sram read and write cycles are inhibited until hsb is returned high by mpu or other external source. during any store operation, rega rdless of how it is initiated, the cy14b104la/cy14b104na c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power-up) during power-up or after any low power condition (v cc cy14b104la, cy14b104na document #: 001-49918 rev. *j page 7 of 25 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power-down cycles. the part comes from the factory with autostore enabled. data protection the cy14b104la/cy14b104na protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14b104la/cy14b104na is in a write mode (both ce and we are low) at power-up, after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against inadvertent writes during power-up or brown out conditions. noise considerations refer to cy application note an1064 . l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [14] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram non-volatile store output data output data output data output data output data output high z active i cc2 [14] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram non-volatile recall output data output data output data output data output data output high z active [14] table 1. mode selection (continued) ce we oe bhe , ble [11] a 15 ?a 0 [12] mode i/o power note 14. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a non-volatile cycle.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 8 of 25 best practices nvsram products have been used effectively for over 27 years. while ease-of-use is one of the product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the non-volatile cells in this nvsram product are delivered from cypress with 0x00 written in all cells. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprogram these valu es. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique nv pattern (that is, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as pa rt of the final system manufac- turing test to ensure these system routines work consistently. power-up boot firmware routines should rewrite the nvsram into the desired state (for example, autostore enabled). while the nvsram is shipped in a pres et state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. the v cap value specified in this datasheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because the nvsram internal algorithm calculates v cap charge and discharge time based on this maximum v cap value. customers that want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection with cypress to unde rstand any impact on the v cap voltage level at the end of a t recall period.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 9 of 25 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 c to +150 c maximum accumulated storage time at 150 c ambient temperature ...................... 1000 h at 85 c ambient temperature ..................... 20 years ambient temperature with power applied .... .............. .............. .......... ?55 c to +150 c supply voltage on v cc relative to v ss ...........?0.5 v to 4.1 v voltage applied to outputs in high z state ..................................... ?0.5 v to v cc + 0.5 v input voltage ........................................?0.5 v to vcc + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ .............. .............. ..... +260 c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch up current ..................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 2.7 v to 3.6 v dc electrical characteristics over the operating range (v cc = 2.7 v to 3.6 v) parameter description test conditions min typ [15] max unit v cc power supply 2.7 3.0 3.6 v i cc1 average v cc current t rc = 20 ns t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) ??70 70 52 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store ??10ma i cc3 average v cc current at t rc = 200 ns, v cc(typ) , 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma). ?35?ma i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??5ma i sb v cc standby current ce > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). standby current level after non-volatile cycle is complete. inputs are static. f = 0 mhz. ??5ma i ix [16] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 ? +1 a input leakage current (for hsb )v cc = max, v ss < v in < v cc ?100 ? +1 a i oz off-state output leakage current v cc = max, v ss < v out < v cc , ce or oe > v ih or bhe /ble > v ih or we < v il ?1 ? +1 a v ih input high voltage 2.0 ? v cc + 0.5 v v il input low voltage v ss ? 0.5 ? 0.8 v v oh output high voltage i out = ?2 ma 2.4 ? ? v v ol output low voltage i out = 4 ma ? ? 0.4 v v cap [17] storage capacitor between v cap pin and v ss , 5 v rated 61 68 180 f notes 15. typical values are at 25 c, v cc = v cc(typ) . not 100% tested. 16. the hsb pin has i out = ?2 a for v oh of 2.4 v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. 17. min v cap value guarantees that there is a sufficient charge available to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within the specified min and max limits. refer application note an43593 for more details on v cap options.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 10 of 25 ac test conditions input pulse levels ................................................... 0 v to 3 v input rise and fall times (10% ?90%) ........................... < 3 ns input and output timing referenc e levels ...................... 1.5 v data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c non-volatile store operations 1,000 k capacitance parameter [18] description test conditions max unit c in input capacitance (except bhe , ble and hsb ) t a = 25 c, f = 1 mhz, v cc = v cc(typ) 7pf input capacitance (for bhe , ble and hsb ) 8pf c out output capacitance (except hsb ) 7 pf output capacitance (for hsb ) 8 pf thermal resistance parameter [18] description test conditions 48-pin fbga 44-pin tsop ii 54-pin tsop ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 46.09 43.3 42.03 c/w jc thermal resistance (junction to case) 7.84 5.56 6.08 c/w ac test loads figure 5. ac test loads 3.0 v output 5 pf r1 r2 789 3.0 v output 30 pf r1 r2 789 for tristate specs 577 577 18. these parameters are guaranteed by design but not tested.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 11 of 25 ac switching ch aracteristics over the operating range parameters [19] description 20 ns 25 ns 45 ns unit cypress parameter alt parameter min max min max min max sram read cycle t ace t acs chip enable access time ? 20 ? 25 ? 45 ns t rc [20] t rc read cycle time 20 ? 25 ? 45 ? ns t aa [21] t aa address access time ? 20 ? 25 ? 45 ns t doe t oe output enable to data valid ? 10 ? 12 ? 20 ns t oha [21] t oh output hold after address change 3?3?3?ns t lzce [22, 23] t lz chip enable to output active 3?3?3?ns t hzce [22, 23] t hz chip disable to output inactive ? 8 ? 10 ? 15 ns t lzoe [22, 23] t olz output enable to output active 0?0?0?ns t hzoe [22, 23] t ohz output disable to output inactive ? 8 ? 10 ? 15 ns t pu [22] t pa chip enable to power active 0?0?0?ns t pd [22] t ps chip disable to power standby ? 20 ? 25 ? 45 ns t dbe ? byte enable to data valid ? 10 ? 12 ? 20 ns t lzbe [22] ? byte enable to output active 0?0?0?ns t hzbe [22] ? byte disable to output inactive ? 8 ? 10 ? 15 ns sram write cycle t wc t wc write cycle time 20 ? 25 ? 45 ? ns t pwe t wp write pulse width 15 ? 20 ? 30 ? ns t sce t cw chip enable to end of write 15 ? 20 ? 30 ? ns t sd t dw data setup to end of write 8 ? 10 ? 15 ? ns t hd t dh data hold after end of write 0?0?0?ns t aw t aw address setup to end of write 15 ? 20 ? 30 ? ns t sa t as address setup to start of write 0?0?0?ns t ha t wr address hold after end of write 0?0?0?ns t hzwe [22, 23, 24] t wz write enable to output disable ? 8 ? 10 ? 15 ns t lzwe [22, 23] t ow output active after end of write 3?3?3?ns t bw ? byte enable to end of write 15 ? 20 ? 30 ? ns switching waveforms figure 6. sram read cycle #1 (address controlled) [20, 21, 25] address data output address valid previous data valid output data valid t rc t aa t oha notes 19. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh and load capacitance shown in figure 5 on page 10 . 20. we must be high during sram read cycles. 21. device is continuously selected with ce , oe and bhe / ble low. 22. these parameters are guaranteed by design but not tested. 23. measured 200 mv from steady state output voltage. 24. if we is low when ce goes low, the outputs remain in the high impedance state. 25. hsb must remain high during read and write cycles.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 12 of 25 figure 7. sram read cycle #2 (ce and oe controlled) [26, 27, 28] figure 8. sram write cycle #1 (we controlled) [26, 28, 29, 30] switching waveforms (continued) address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce notes 26. bhe and ble are applicable for 16 configuration only. 27. we must be high during sram read cycles. 28. hsb must remain high during read and write cycles. 29. if we is low when ce goes low, the outputs remain in the high impedance state. 30. ce or we must be > v ih during address transitions.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 13 of 25 figure 9. sram write cycle #2 (ce controlled) [31, 32, 33, 34] figure 10. sram write cycle #3 (bhe and ble controlled) [31, 32, 33, 34] switching waveforms (continued) data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sce t sa t bw t ha t aw t pwe notes 31. bhe and ble are applicable for 16 configuration only. 32. if we is low when ce goes low, the outputs remain in the high impedance state. 33. hsb must remain high during read and write cycles. 34. ce or we must be > v ih during address transitions.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 14 of 25 autostore/power-up recall over the operating range parameter description 20 ns 25 ns 45 ns unit min max min max min max t hrecall [35] power-up recall duration ? 20 ? 20 ? 20 ms t store [36] store cycle duration ? 8 ? 8 ? 8 ms t delay [37] time allowed to complete sram write cycle ?20?25?25ns v switch low voltage trigger level ? 2.65 ? 2.65 ? 2.65 v t vccrise [38] v cc rise time 150 ? 150 ? 150 ? s v hdis [38] hsb output disable voltage ? 1.9 ? 1.9 ? 1.9 v t lzhsb [38] hsb to output active time ? 5 ? 5 ? 5 s t hhhd [38] hsb high active time ? 500 ? 500 ? 500 ns switching waveforms figure 11. autostore or power-up recall [39] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 36 36 40 40 notes 35. t hrecall starts from the time v cc rises above v switch . 36. if an sram write has not taken place since the last non-volatile cycle, no autostore or hardware store takes place. 37. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 38. these parameters are guaranteed by design but not tested. 39. read and write cycles are ignored during store, recall, and while v cc is below v switch . 40. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 15 of 25 software controlled store/recall cycle over the operating range parameter [41, 42] description 20 ns 25 ns 45 ns unit min max min max min max t rc store/recall initiation cycle time 20 ? 25 ? 45 ? ns t sa address setup time 0 ? 0 ? 0 ? ns t cw clock pulse width 15?20?30?ns t ha address hold time 0 ? 0 ? 0 ? ns t recall recall duration ? 200 ? 200 ? 200 s switching waveforms figure 12. ce and oe controlled software store/recall cycle [42] figure 13. autostore enable/disable cycle t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb (store only) dq (data) rwi t delay note 43 t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note 43 notes 41. the software sequence is clocked with ce controlled or oe controlled reads. 42. the six consecutive addresses must be read in the order listed in table 1 on page 6 . we must be high during all six consecutive cycles. 43. dq output data at the sixth read may be invalid since the output is disabled at t delay time.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 16 of 25 hardware store cycle over the operating range parameter description 20 ns 25 ns 45 ns unit min max min max min max t dhsb hsb to output active time when write latch not set ? 20 ? 25 ? 25 ns t phsb hardware store pulse width 15 ? 15 ? 15 ? ns t ss [44, 45] soft sequence processing time ? 100 ? 100 ? 100 s switching waveforms figure 14. hardware store cycle [46] figure 15. soft sequence processing [44, 45] t phsb t phsb t delay t dhsb t delay t store t hhhd t lzhsb write latch set write latch not set hsb (in) hsb (out) dq (data out) rwi hsb (in) hsb (out) rwi hsb pin is driven high to v c c only by internal sram is disabled as long as hsb (in) is driven low . hsb driver is disabled t dhsb 100 kohm resistor, address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw notes 44. this is the amount of time it takes to take action on a soft sequence command. v cc power must remain high to effectively register command. 45. commands such as store and recall lock out i/o until operation is complete which further incr eases this time. see the specif ic command. 46. if an sram write has not taken place since the last non-v olatile cycle, no autostore or hardware store takes place.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 17 of 25 truth table for sram operations hsb should remain high for sram operations. table 2. truth table for 8 configuration ce we oe inputs/outputs [47] mode power h x x high z deselect/power-down standby l h l data out (dq 0 ?dq 7 ); read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ); write active table 3. truth table for 16 configuration ce we oe bhe [48] ble [48] inputs/outputs [47] mode power h x x x x high z deselect/power-down standby l x x h h high z output disabled active lhllldata out (dq 0 ?dq 15 ) read active l h l h l data out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high z read active l h l l h data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high z read active l h h l l high z output disabled active l h h h l high z output disabled active l h h l h high z output disabled active llxlldata in (dq 0 ?dq 15 ) write active llxhldata in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high z write active llxlhdata in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high z write active notes 47. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 48. bhe and ble are applicable for 16 configuration only.
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 18 of 25 ordering information speed (ns) ordering code package diagram package type operating range 20 cy14b104la-zs20xit 51-85087 44-pin tsop ii industrial cy14b104la-zs20xi 51-85087 44-pin tsop ii cy14b104na-zs20xit 51-85087 44-pin tsop ii cy14b104na-zs20xi 51-85087 44-pin tsop ii cy14b104na-ba20xit 51-85128 48-ball fbga cy14b104na-ba20xi 51-85128 48-ball fbga 25 CY14B104LA-ZS25XIT 51-85087 44-pin tsop ii cy14b104la-zs25xi 51-85087 44-pin tsop ii cy14b104la-ba25xit 51-85128 48-ball fbga cy14b104la-ba25xi 51-85128 48-ball fbga cy14b104na-zs25xit 51-85087 44-pin tsop ii cy14b104na-zs25xi 51-85087 44-pin tsop ii cy14b104na-ba25xit 51-85128 48-ball fbga cy14b104na-ba25xi 51-85128 48-ball fbga cy14b104na-ba25i 51-85128 48-ball fbga cy14b104na-zsp25xit 51-85160 54-pin tsop ii cy14b104na-zsp25xi 51-85160 54-pin tsop ii 45 cy14b104la-zs45xit 51-85087 44-pin tsop ii cy14b104la-zs45xi 51-85087 44-pin tsop ii cy14b104la-ba45xit 51-85128 48-ball fbga cy14b104la-ba45xi 51-85128 48-ball fbga cy14b104na-zs45xit 51-85087 44-pin tsop ii cy14b104na-zs45xi 51-85087 44-pin tsop ii cy14b104na-ba45xit 51-85128 48-ball fbga cy14b104na-ba45xi 51-85128 48-ball fbga cy14b104na-zsp45xit 51-85160 54-pin tsop ii cy14b104na-zsp45xi 51-85160 54-pin tsop ii
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 19 of 25 ordering code definitions option: t - tape & reel blank - std. speed: 20 - 20 ns 25 - 25 ns data bus: l - 8 n - 16 density: 104 - 4 mb voltage: b - 3.0 v cypress cy 14 b 104 l a - zs 20 x i t nvsram 14 - package: ba - 48-ball fbga zs - 44-pin tsop ii 45 - 45 ns x - pb-free blank - sn pb die revision: blank - no rev a - 1 st rev i - industrial ( ?40 to 85 c ) temperature: zsp - 54-pin tsop ii
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 20 of 25 package diagrams figure 16. 44-pin tsop ii, 51-85087 51-85087 *d
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 21 of 25 figure 17. 48-ball fbga (6 10 1.2 mm), 51-85128 package diagrams (continued) 51-85128 *f
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 22 of 25 figure 18. 54-pin tsop ii (22.4 11.84 1.0 mm), 51-85160 package diagrams (continued) 51-85160 *c
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 23 of 25 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance fbga fine-pitch ball grid array hsb hardware store busy i/o input/output nvsram non-volatile static random access memory oe output enable rohs restriction of hazardous substances rwi read and write inhibited sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius hz hertz khz kilohertz k kilo-ohm mhz megahertz a microampere f microfarad s microsecond ma milliampere ms millisecond ns nanosecond ohm % percent pf picofarad v volt w watt
cy14b104la, cy14b104na document #: 001-49918 rev. *j page 24 of 25 document history page document title: cy14b104la/cy14b104na, 4-mbit (512 k 8/256 k 16) nvsram document number: 001-49918 revision ecn orig. of change submission date description of change ** 2606696 gvch / pyrs 11/13/08 new datasheet *a 2672700 gvch / pyrs 03/12/09 added best practices added cy14b104na-ba25i part number added footnote12 for hz/lz parameters *b 2710274 gvch / aesa 05/22/09 moved datasheet status from preliminary to final updated autostore operation updated i sb test condition updated footnote 9 referenced footnote 12 to v ccrise , t hhhd and t lzhsb parameters updated v hdis parameter description updated figure 12 *c 2738586 gvch 07/15/09 page 4: updated hardware store operation description page 5: updated software store description updated t delay parameter description updated footnote 20 added footnote 25 referenced footnote 25 to figure 12 and figure 13 *d 2758397 gvch / aesa 09/01/09 removed commercial tem perature related specifications *e 2773362 gvch 10/06/09 ordering information: added 20 ns part in a 48-fbga package *f 2826364 gvch / pyrs 12/11/09 changed store cycles to qu antumtrap from 200k to 1 million *g 2923475 gvch / aesa 04/27/2010 table 1 : added more clarity on hsb pin operation hardware store operation : added more clarity on hsb pin operation table 1 : added more clarity on bhe /ble pin opeartion updated hsb pin operation in figure 11 updated footnote 22 updated package diagrams and sales, solutions, and legal information . *h 3132368 gvch 01/10/2011 48-ball fbga package: 16 mb address expansion is not supported updated input capacitance for bhe and ble pin updated input and output capacitance for hsb pin fixed typo in figure 11 added acronyms table and document conventions table. *i 3305495 gvch 07/07/2011 updated dc electrical characteristics (added note 17 and referred the same note in v cap parameter). updated ac switching characteristics (added note 19 and referred the same note in parameters). updated thermal resistance (values of ja for all packages). updated package diagrams . *j 3389991 gvch 09/30/2011 updated package diagrams
document #: 001-49918 rev. *j revi sed september 30, 2011 page 25 of 25 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14b104la, cy14b104na ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY14B104LA-ZS25XIT

	To Download CY14B104LA-ZS25XIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .